1. Field of the Invention
The present invention relates to a charge pump and, more particularly, to a charge pump capable of preventing from reverse current, thereby generating a pumping voltage with high efficiency.
2. Description of the Related Art
FIG. 1 is a detailed circuit diagram showing a conventional charge pump 10. NMOS transistors N1 and N2 have first current electrodes together coupled to a supply voltage source Vin. A control electrode of the NMOS transistor N1 is coupled to a second current electrode of the NMOS transistor N2 while a control electrode of the NMOS transistor N2 is coupled to a second current electrode of the NMOS transistor N1. A capacitor C1 has a first electrode coupled to the second current electrode of the NMOS transistor N1 while a capacitor C2 has a first electrode coupled to the second current electrode of the NMOS transistor N2.
An NMOS transistor N3 has a first current electrode coupled to the second current electrode of the NMOS transistor N2 while an NMOS transistor N4 has a first current electrode coupled to the second current electrode of the NMOS transistor N1. A control electrode of the NMOS transistor N3 is coupled to a second current electrode of the NMOS transistor N4 while a control electrode of the NMOS transistor N4 is coupled to a second current electrode of the NMOS transistor N3. A capacitor C3 has a first electrode coupled to the second current electrode of the NMOS transistor N3 while a capacitor C4 has a first electrode coupled to the second current electrode of the NMOS transistor N4.
An NMOS transistor N5 has a first current electrode coupled to the second current electrode of the NMOS transistor N3. Also, the NMOS transistor N5 has a control electrode coupled to its own first current electrode, forming a diode-coupled transistor. A pumping voltage Vpp of the charge pump 10 is asserted at a second current electrode of the NMOS transistor N5.
Under the control of clock signals CLK1 and CLK2, the conventional charge pump 10 performs a function of boosting voltage through charge transferring operations. Referring to FIG. 2(a), the clock signals CLK1 and CLK2 are a same-stage complementary pair of pulse trains with equal amplitude. In addition, the clock signals CLK1 and CLK2 are so designed as to be non-overlapping with respect to each other for avoiding synchronous occurrence of a high level. Typically, the amplitude of the clock signals CLK1 and CLK2 alternately swings between the supply voltage source Vin and a ground potential. As shown in FIG. 1, the clock signals CLK1 is applied to both of second electrodes of the capacitors C1 and C3 while the clock signals CLK2 is applied to both of second electrodes of the capacitors C2 and C4.
Hereinafter is described in detail an operation of the conventional charge pump 10. For understanding the operation of the conventional charge pump 10, it is assumed as an initial condition that the first electrodes of the capacitors C1 and C2 are both at a voltage of Vin. When the clock signal CLK1 is at the low level and the clock signal CLK2 is at the high level, such as a time interval A shown in FIG. 2(a), the first electrode of the capacitor C2 is pushed upwardly to a voltage of 2*Vin, turning on the transistor N1. As a result, the supply voltage source Vin charges the capacitor C1, sustaining the first electrode of the capacitor C1 at the voltage of Vin. Subsequently, when the clock signal CLK1 is at the high level and the clock signal CLK2 is at the low level, such as a time interval B shown in FIG. 2(a), the first electrode of the capacitor C2 is pulled downwardly to a voltage of Vin and the first electrode of the capacitor C1 is pushed upwardly to a voltage of 2*Vin, turning on the transistor N2. As a result, the supply voltage source Vin charges the capacitor C2, sustaining the first electrode of the capacitor C2 at the voltage of Vin.
Therefore, a first pumping stage of the charge pump 10 is constructed by the transistors N1 and N2 with the capacitors C1 and C2 under the control of the clock signals CLK1 and CLK2, supplying a first stage pumping voltage 2*Vin to a next pumping stage alternately through the first electrodes of the capacitors C1 and C2.
Similarly, it is assumed as an initial condition that the first electrodes of the capacitors C3 and C4 are both at a voltage of 2*Vin. When the clock signal CLK1 is at the low level and the clock signal CLK2 is at the high level, such as the time interval A shown in FIG. 2(a), the first electrode of the capacitor C4 is pushed upwardly to a voltage of 3*Vin, turning on the transistor N3. As a result, the first electrode of the capacitor C2 supplies the capacitor C3 with the first stage pumping voltage 2*Vin, sustaining the first electrode of the capacitor C3 at the voltage of 2*Vin. Subsequently, when the clock signal CLK1 is at the high level and the clock signal CLK2 is at the low level, such as the time interval B shown in FIG. 2(a), the first electrode of the capacitor C4 is pulled downwardly to a voltage of 2*Vin and the first electrode of the capacitor C3 is pushed upwardly to a voltage of 3*Vin, turning on the transistor N4. As a result, the first electrode of the capacitor C1 supplies the capacitor C4 with the first stage pumping voltage 2*Vin, sustaining the first electrode of the capacitor C4 at the voltage of 2*Vin.
Therefore, a second pumping stage of the charge pump 10 is constructed by the transistors N3 and N4 with the capacitors C3 and C4 under the control of the clock signals CLK1 and CLK2, supplying a second stage pumping voltage 3*Vin to an output stage alternately through the first electrodes of the capacitors C3 and C4.
The transistor N5 serves as the output stage of the charge pump 10, functioning as a diode for only allowing the charge pump 10 to output the pumping voltage Vpp. Due to the effect of the transistor N5, the pumping voltage Vpp is subjected to a voltage loss of a forward bias diode drop, required to turn on the transistor N5, from the voltage of the first electrode of the capacitor C3.
Under adverse effects of reverse current (or reverse charge transfer), the conventional charge pump 10 fails to achieve an efficient voltage-converting characteristic. In the prior art, the reverse current occurs in two situations where: (1) the clock signals are at steady states and (2) the clock signals make transitions from the high level to the low level or from the low level to the high level.
Firstly is described the reverse current problem the charge pump 10 is subjected to when the clock signals are at steady states. When the clock signal CLK1 is at the high level and the clock signal CLK2 is at the low level, such as the time interval B shown in FIG. 2(a), the second current electrode of the transistor N1 is at the voltage of 2*Vin, the second current electrode of the transistor N2 is at the voltage of Vin, the second current electrode of the transistor N3 is at the voltage of 3*Vin, the second current electrode of the transistor N4 is at the voltage of 2*Vin. Therefore, the transistor N3 has the control electrode at the voltage of 3*Vin and the first current electrode at the voltage of Vin, resulting in being turned on. Since the transistor N2 is also turned on at this moment, a steady-state reverse current is discharged from the first electrode of the capacitor C3, which is at the voltage of 3*Vin, flowing through the transistors N3 and N2 sequentially, and back to the supply voltage source Vin. In such case that the steady-state reverse current exists, the charge stored in the capacitor C3 cannot be fully transferred to the transistor N5, i.e. the output stage of the charge pump 10, resulting in a reduced efficiency of generating the pumping voltage Vpp.
Followed is a description of the reverse current problem the charge pump 10 is subjected to when the clock signals make transitions. Although the capacitors C1 and C3 are wired to receive the same clock signal CLK1 and the capacitors C2 and C4 are wired to receive the same clock signal CLK2 in the description set forth, an amount of time delay is inevitably produced in the clock signals CLK1 and CLK2 due to signal distribution along the clock lines in practical circuit applications. If the time delay is considered, the capacitor C3 actually receives a clock signal CLK3 as shown in FIG. 2(b), which is a delayed signal from the clock signal CLK1, and the capacitor C4 actually receives a clock signal CLK4 as shown in FIG. 2(b), which is a delayed signal from the clock signal CLK2.
When the clock signals CLK1 and CLK3 are both at the low level and the clock signals CLK2 and CLK4 are both at the high level, such as a time interval A shown in FIG. 2(b), the second current electrode of the transistor N1 is at the voltage of Vin, the second current electrode of the transistor N2 is at the voltage of 2*Vin, the second current electrode of the transistor N3 is at the voltage of 2*Vin, the second current electrode of the transistor N4 is at the voltage of 3*Vin. Subsequently, when the clock signal CLK2 makes a transition from the high level to the low level, the clock signal CLK4 still retains the high level due to the time delay, such as a time interval C shown in FIG. 2(b). At this moment, both of the clock signals CLK1 and CLK3 stay at the low level because of the non-overlapping arrangement described above. In this case, the first current electrode of the transistor N3 since coupled to the second current electrode of the transistor N2 is pulled downwardly to a voltage of Vin. Because the control electrode of the transistor N3 is at the voltage of 3*Vin, the transistor N3 is turned on such that a transition-state reverse current is discharged from the first electrode of the capacitor C3, which is at the voltage of 2*Vin, flowing through the transistor N3 and back to the first electrode of the capacitor C2. In such case that the transition-state reverse current exists, the first electrode of the capacitor C3 cannot be fully charged to the desired voltage of 2*Vin, causing that the first electrode of the capacitor C3 cannot be fully pushed upwardly to the desired voltage of 3*Vin when the clock signal CLK3 subsequently makes a transition from the low level to the high level, such as a time interval B shown in FIG. 2(b). As a result, the efficiency of generating the pumping voltage Vpp by the charge pump 10 is reduced.